The invention relates to a method for performing a short-circuit and overload disconnection using a semiconductor component. The invention relates in particular to a method for performing a disconnection using active limiters in the form of JFETs (Junction Field Effect Transistors) based on silicon carbide (SiC). The semiconductor component has a drain, a source and a gate and a prescribed gate-source voltage is applied to it. The semiconductor has a prescribed current flow, and as a result, a voltage drops across the component. In addition, the invention also relates to an apparatus for carrying out the method.
The actual short-circuit as well as the overload operating situation are both referred to by the term xe2x80x9cshort-circuitxe2x80x9d below. In such operating situations, the aim is to turn off the current in the electrical power supply as quickly as possible.
During a short-circuit, unavoidable thermal and electrodynamic stresses in electrical or electronic components, which are used for the process of turning off or disconnecting, are linked to the short-circuit""s recognition time and to the time required for the disconnection process. Semiconductor components specifically based on SiC are currently being developed whose propertiesxe2x80x94such as low current flow losses, overload capacity, high reverse voltagexe2x80x94will in the future permit a short-circuit disconnection which limits the current and is virtually instantaneous even in a practical operations. This is associated with a drastic reduction in the forward current and the resistive heating integral. If, by using comparative simulation calculations, it were possible to find suitable descriptive equations for the SiC-based semiconductor components, then these equations could be used as a basis to derive methods ensuring a short-circuit disconnection which poses no risk to the semiconductor components or to the power supply.
European Patent No. EP 0 717 887 B1, which corresponds to U.S. Pat. No. 5,808,327, discloses an AC power controller which makes use of two serially reverse-connected semiconductor components on silicon carbide (SiC). In addition, German Published, Non-Prosecuted Patent Application DE 195 48 443 A1, which corresponds to U.S. Pat. No. 6,034,385, describes a semiconductor configuration for limiting a current based on SiC technology. U.S. Pat. No. 6,034,385 essentially describes the structure of a component having individual semiconductor regions. Furthermore, U.S. Pat. No. 4,228,367 discloses a high-speed circuit for analog signals with semiconductor components, in which the components used are JFETs, the circuit having assigned thereto fault monitoring devices which use the current-limiting effect of the JFETs, which act as limiters. The components are conventional field-effect transistors based on silicon (Si).
It is accordingly an object of the invention to provide a method and an apparatus for a short-circuit and overload disconnection which overcome the above-mentioned disadvantages of the heretofore-known methods and devices of this general type and which use semiconductor components based on SiC technology and allow current-carrying lines to be disconnected as quickly as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for performing a short-circuit and overload disconnection with a semiconductor component, which includes the steps of:
providing a semiconductor component having a drain, a source and a gate, the semiconductor component having a gate-source voltage UGS applied thereto, having a current IJFET flowing therethrough, and having a voltage UJFET dropping across the semiconductor component;
adjusting, in an operating situation, the gate-source voltage UGS at the semiconductor component, in dependence of the current IJFET, such that, after charge carriers in the semiconductor component are depleted, the voltage UJFET assumes a highest possible value still uncritical for the semiconductor component and for a circuit to be disconnected; and
using, for the step of adjusting the gate-source voltage UGS, an algorithm in the form of       U    GS    =            U      on        ⁡          [              1        -                                                            I                JFET                            ⁢                              (                t                )                                                                    G                JFET                            ⁢                              (                                  U                  JFET                                )                                                        ]      
where Uon denotes a switching voltage, IJFET(t) denotes the current IJFET in dependence of a time t and GJFET denotes a function dependent only on the voltage UJFET dropping across the semiconductor component.
In accordance with another mode of the invention, an active limiter in the form of a JFET based on silicon carbide is used as the semiconductor component.
In accordance with yet another mode of the invention, the current IJFET is used for at least one of an open-loop control and a closed-loop control of the semiconductor component.
In accordance with a further mode of the invention, the voltage UJFET is recorded as an actual value at the semiconductor component. The actual value is used for determining a closed-loop control signal, and, with the closed-loop control signal, a parameter drift of the semiconductor component is compensated.
In accordance with another mode of the invention, open-loop control signals and closed-loop control signals are determined from at least one of the current IJFET and the voltage UJFET. The open-loop control signals and the closed-loop control signals are superimposed for controlling the semiconductor component.
With the objects of the invention in view there is also provided, in combination with a short-circuit and overload circuitry and a semiconductor component connected to the short-circuit and overload circuitry, the semiconductor component having a drain, a source and a gate, the semiconductor component having a gate-source voltage UGS applied thereto, a current IJFET flowing therethrough, and a voltage UJFET dropping between the drain and the source, an apparatus for performing a short-circuit and overload disconnection, including:
a processor operatively connected to the semiconductor component for processing measured values and for early recognizing one of a short-circuit and an overload;
the processor being programmed to:
adjust, in an operating situation, the gate-source voltage UGS at the semiconductor component, in dependence of the current IJFET, such that, after a charge carrier depletion in the semiconductor component, the voltage UJFET assumes a highest possible value still uncritical for the semiconductor component and for the short-circuit and overload circuitry to be disconnected;
use an algorithm in the form of       U    GS    =            U      on        ⁡          [              1        -                                                            I                JFET                            ⁢                              (                t                )                                                                    G                JFET                            ⁢                              (                                  U                  JFET                                )                                                        ]      
for adjusting the gate-source voltage UGS, where Uon denotes a switching voltage, IJFET(t) denotes the current IJFET in dependence of a time t and GJFET denotes a function dependent only on the voltage UJFET dropping between the drain and the source; and
drive the semiconductor component as an active limiter for supervising the short-circuit and overload circuitry.
In other words, the apparatus according to the invention is configured for carrying out the method of the invention. The apparatus has a processor for processing measured values, and the processor is configured for an early recognition of the short-circuit or of the overload and drives or corrects a semiconductor component as an active limiter for monitoring a short-circuit and overload circuitry.
In accordance with another feature of the invention, the processor is configured to carry out a regulating function, in particular a PI regulating function.
In accordance with another feature of the invention, the processor is configured to carry out an open-loop control function and/or a closed-loop control function based on the algorithm for driving or controlling the semiconductor component.
In accordance with a further feature of the invention, the processor includes a first unit for producing a regulating signal and a second unit for producing a reference variable with the algorithm; and the processor forms a summation signal from the regulating signal and the reference variable for driving the semiconductor component as an active limiter.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and an apparatus for performing a short-circuit and overload disconnection it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.